CMOS image sensor having a chopper-type comparator to perform analog correlated double sampling

ABSTRACT

A CMOS image sensor performing an analog correlated double sampling is disclosed. The CMOS image sensor may include an image capture device for capturing an image for analog image signal from an object an analog-to-digital converter for converting the analog image signal to a digital value using a ramp signal. In such an arrangement the analog-to-digital converter may includes a chopper-type comparator receiving the analog image signal and the ramp signal and a capacitor for receiving a start voltage of the ramp signal and charging a voltage level corresponding the start voltage of the ramp signal in a reset mode and for receiving a down-ramping signal of the ramp signal in a count mode in order to remove an device offset voltage. The analog-to-digital converter may also include a ramp signal generator providing the ramp signal to the analog-to-digital converter.

TECHNICAL FIELD

The invention relates to image sensors and, more particularly, to acomplimentary metal oxide semiconductor (CMOS) image sensor able toperform analog correlated double sampling (CDS).

DESCRIPTION OF THE RELATED ART

Generally, an image sensor is an apparatus that captures images fromobjects by using the property that silicon semiconductors react withvisible light. Most previous image sensors have used charge coupleddevices (CCD) as image capturing devices.

However, current CMOS technology has matured to the point that theimagers implemented using CMOS transistors are becoming more popular.CMOS imagers have an advantage over CCD imagers in that supplementaryanalog and digital circuits can be integrated together with a CMOS imagesensing portion on a single chip with very low cost, which makes itpossible for the CMOS image sensor to have analog-to-digital conversioncircuits and other image processing logic circuits integrated on asingle imager.

The on-chip analog-to-digital conversion circuits are comprised of asmany comparators as columns in a pixel array of the CMOS image sensorand the picture quality of the CMOS image sensor depends largely on thequality of these comparators that convert analog pixel signals intodigital signals.

FIG. 1 is a block diagram illustrating a conventional CMOS image sensorwith the function of correlated double sampling. As shown in FIG. 1, theconventional CMOS image sensor includes a pixel array 100, a comparatorarray 200, a line buffer 300, a ramp signal generator 400, a digitalcontroller 500 and a row decoder 600. The pixel array 100 has unitpixels arranged in the Bayer Pattern and the ramp signal generator 400generates a ramp signal (as a reference signal for comparison) that isrequired to find a digital value according to an input analog signalfrom the pixel. The line buffer 300 consists of 4 arrays of dynamiclatch circuits to store the digital value from the comparator array 200and the digital controller 500 controls the row decoder 600, the linebuffer 300 and the ramp generator 400, and performs additional imagesignal processing. The row decoder 600 selects a specific row of thepixel array 100 to read out the analog pixel signals under the controlof the digital controller 500.

When the row decoder 600 selects a row line of the pixel array 100, theanalog pixel signals are input to the comparator array 200, along withthe ramp signal produced by the ramp signal generator 400. Thecomparators of the comparator array 200 compare the analog pixel signalswith the ramp signal to find the digital pixel signals foranalog-to-digital conversion.

The comparator array 200 has as many comparators as columns in the pixelarray 100 and these comparators perform the analog-to-digital conversionon a row-by-row basis. The converted digital data (signals) are storedin the line buffer 300 on a column by column basis. The digital pixelsignals stored in the line buffer 300 are then transferred to thedigital controller 500, which performs the image processing on them andthen outputs the digital image signals through the output pins of theCMOS image sensor.

FIG. 2 is a block diagram illustrating the analog-to-digital conversioncircuits of a column of the conventional CMOS image sensor in FIG. 1.Additionally, FIG. 3 is a waveform of ramp signal to be compared withthe analog pixel signal. There are two ramps in the overall ramp signal,which actually perform two analog-to-digital conversions for correlateddouble sampling (CDS).

Referring to FIG. 2, analog-to-digital conversion is carried out by acomparator 210, which is a so-called column ADC(analog-to-digitalconverter), to compare the analog signal obtained from a unit pixel 110with the ramp signal from the ramp signal generator 400. The resultingoutput signal of the comparator 210 controls the latch 310 to catch andkeep the digital gray code that becomes a digital pixel signal in graycode. The gray counter (not shown) is used for minimal error owing tothe asynchronous output signal of the comparator 210.

The unit pixel 110 includes a photodiode 32 to generate a voltage froman image of an object; a transfer transistor Tx to cut the current pass,which will give the photodiode the chance to collect the photo-generatedelectrons to produce the pixel voltage; and a source-follower (or drive)transistor Dx driven by the photodiode voltage transferred through thetransfer transistor Tx, which has a function to safely transfer thepixel voltage to the comparator. The unit pixel 110 also includes areset transistor Rx that has two functions, to flush out all theelectrons in the photodiode and to apply a reset signal to a gate of thesource-follower transistor Dx; a selection transistor Sx to let thesource-follower voltage out to a comparator 210; and a bias currentsource Is to supply the bias current to the source-follower transistorDx.

To reduce fixed pattern noise (FPN), correlated double sampling (CDS) isused when reading the pixel data. CDS includes two phases, reading resetvoltage and reading data voltage. To read the reset voltage, thetransfer transistor Tx should be turned off, the reset transistor Rx isto be on for a time long enough to charge the floating node connected tothe gate of source-follower transistor Dx up to VDD and then off, andthe select transistor Sx must be on to apply the output voltage of thesource-follower to the comparator. After the completion ofAD(analog-to-digital) conversion cycle, the digital value of the pixelreset voltage is stored in the reset bank of line buffer.

To read the data voltage, the transfer transistor Tx is turned on forsome time long enough to complete the process of charge sharing of thephotodiode and the floating node of the Dx transistor and then off, andthe select transistor Sx is turned on to apply the data voltage of thetransistor Dx to the comparator for AD conversion. During the secondphase, the Rx transistor is always off. After the second phase, thedigital value of pixel data is stored in the data bank of line buffer.The actual CDS process is carried out by the digital control block 500,which digitally subtracts the reset value from the data value, to filterout all the signal sources of fixed pattern noise.

The process of AD conversion of this imager is simple. When the rampgenerator 400, a simple switched-capacitor integrator, starts togenerate a ramp signal, the digital control block 500 starts to countthe gray code and the gates of digital latches in the line buffer 300controlled by the comparator 200 that compares the ramp signal (+) andthe pixel voltage (−), opens the gates of latches when the ramp signalis higher than the pixel voltage, and closes the gates when it is lowerare open and ready for the digital latches to follow the codes of thegray counter. The comparator 200 then closes the gates of latches in theline buffer 300 when the ramp signal is the same as, or lower than, thepixel voltage, which means that the latches of the column controlled bythe comparator of that column keep the digital value in gray codeconverted from the analog pixel voltage. In other words, the rampgenerator scans from the voltage higher than the maximum possible pixelvoltage to the voltage lower than the minimum possible pixel voltage sothat the comparator can convert all the analog pixel voltages to digitalcodes. The gray codes in the line buffer are then transferred to thedigital control block 500, converted to the binary codes, and processedwith the CDS operation after the completion of AD conversion of a fullrow of pixel voltages.

FIG. 4 is a circuit diagram of the conventional comparator of FIG. 2.However, the detailed description will be omitted because this CMOSdifferential amplifier is well known to those skilled in the art towhich the subject matter pertains.

Typically, a CMOS differential amplifier has an offset voltage and, forthe case that a few hundreds of comparators are implemented with suchdifferential amplifiers, the offset voltages of the comparators are notuniform. Therefore, these mismatches of offset voltages of comparatorsresult in the fixed pattern noise in the image captured by this imager.That is why CDS is important in this type of AD conversion. But thetraditional CDS performed in the images of FIG. 1 is done digitally,which causes quantization noise.

FIG. 5 is a block diagram of the line buffer 300 of FIG. 1. Referring toFIG. 5, two registers of 8-bit or 9-bit latch cells are required for onepixel value owing to CDS operation.

One weak point that the comparator implemented with the CMOSdifferential amplifier has is that when it is not actually comparing,the static bias currents are still flowing, which results in poor powerefficiency. Poor efficiency is a serious defect when applying sensors tomobile applications.

Another weak point is that it is impossible to use a specific gammacorrection for the pixel analog signals because the start voltage of theramp signal is different from one another due to the various offsetvoltages of the comparators.

SUMMARY OF THE INVENTION

The disclosed CMOS image sensor may include an image capturer forcapturing an image for analog image signal from an object and ananalog-to-digital converter that converts the analog image signal to adigital value using a ramp signal. In such an arrangement, theanalog-to-digital converter may include a chopper-type comparatorreceiving the analog image signal and the ramp signal and a firstcapacitor that receives a start voltage of the ramp signal and charginga voltage level corresponding the start voltage of the ramp signal in areset mode and for receiving a down-ramping signal of the ramp signal ina count mode in order to remove an device offset voltage. The CMOS imagesensor may also include a ramp signal generator providing the rampsignal to the analog-to-digital converter.

In a rest mode, the start voltage of the ramp signal is charged in thefirst capacitor and a reset voltage of the image capturer issimultaneously charged in the chopper-type comparator. In a chargetransfer mode, the analog image signal from the image capturer isprovided to the chopper-type comparator. In a count mode, thedown-ramping signal of the ramp signal is provided to the chopper-typecomparator in a count mode.

The disclosed apparatus may use analog correlated double sampling, whichthe CDS is carried out based on analog signals, rather than onconventional digital correlated double sampling carried out afterconverting analog signals from a pixel to digital signals.

In the disclosed apparatus, an analog signal and an offset voltage froma pixel of the CMOS image sensor are stored in a second capacitor, theramp signal and the offset voltage are stored in a third capacitor, andthen the offset voltage is removed by a switching operation between thesecond and third capacitors.

Also disclosed is a a method for removing a device offset voltage in aCMOS image sensor. The method may include charging a start voltage of aramp signal in a capacitor and simultaneously charging a rest voltage ofan image capturer in a chopper-type comparator in a reset mode andproviding to the chopper-type comparator an analog image signal from theimage capturer in a charge transfer mode. The method may also includeproviding a down-ramping signal of the ramp signal to the chopper-typecomparator in a count mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a conventional CMOS image sensorwith a correlated double sampling;

FIG. 2 is a block diagram illustrating the analog-to-digital conversioncircuit of the conventional CMOS image sensor of FIG. 1;

FIG. 3 is a waveform of ramp signal with an analog signal from a pixelin the correlated double sampling (CDS);

FIG. 4 is a circuit diagram of a conventional comparator of FIG. 2;

FIG. 5 is a block diagram of the line buffer of FIG. 1;

FIG. 6 is a circuit diagram illustrating a chopper-type comparator to beemployed in a CMOS image sensor;

FIG. 7 is a transfer curve of the inverter amplifier illustrating aclamp voltage induced in capacitors of FIG. 6;

FIG. 8 is a circuit diagram illustrating a CMOS image sensor having thechopper-type comparator; and

FIG. 9 is a timing chart useful in operating the chopper-type comparatorof FIG. 8.

DETAILED DESCRIPTION

Hereinafter, the disclosed apparatus will be described in detailreferring to the accompanying drawings.

Referring to FIG. 6, a chopper-type comparator, which the disclosedapparatus employs, includes switches S1 and S2 to selectively connectinput signal Vn or Vo to node A, a first stage 10 having an invertingamplifier IN1 and a switch S3 connected in parallel to the invertingamplifier IN1 and a capacitor C1 connected between node A and the firststage 10. The chopper-type comparator may also include a second stage 20having an inverting amplifier IN12 and a switch S4 connected in parallelto the inverting amplifier IN12 and a capacitor C2 connected between thefirst and second stages 10 and 20. The capacitor C1 stores a clampvoltage of the first stage 10 and the capacitor C2 stores a clampvoltage of the second stage 20.

FIG. 7 is a waveform illustrating the clamp voltage induced in thecapacitor of FIG. 6. If short circuits are respectively formed betweenthe input and output terminals of the inverting amplifiers IN1 and IN2through the switches S3 and S4, clamp voltages of the invertingamplifiers IN1 and IN2 are induced.

As mentioned above, the chopper-type comparator disclosed hereinincludes many switches S1 to S4. The switching operation of the switchesS1 to S4 makes an offset voltage caused by charge injection as thefollowing equation:Voffset=Vth/(A1*A2)where Vth is a logic threshold voltage to subsequently connected nextdigital circuit and A1 and A2 are gains of the first and second stages,respectively. However, this offset voltage is weaker than that in theconventional differential amplifier. Further, the larger the size of thefirst and second stages 10 and 20, the smaller the offset voltage.

It is possible to reduce the offset voltage by increasing the gains ofthe first and second stages 10 and 20 and the fixed pattern noise can beconsiderably reduced by the smaller offset voltage.

Referring to FIG. 8, the CMOS image sensor includes a chopper-typecomparator 220, a unit pixel 120, a ramp signal generator 410, a latchcircuit 320 and a counter 510 to calculate a digital value correspondingto an analog signal (typically, the counter is provided in a digitalcontroller of the CMOS image sensor). In order to implement thecorrelated double sampling (CDS), the chopper-type comparator 220 has anadditional capacitor C3 in the input terminal of the ramp signal so thatthe fixed pattern noise caused between the pixels may be improved.

Referring to FIGS. 8 and 9, the chopper-type comparator 220 carries outthe comparison through three steps. First, if a transfer transistor Txis set to be turned off and a reset transistor Rx and a selectiontransistor Sx are set to be turned on, a reset level (Vrest) is inducedat a source-follower transistor Dx and a voltage Vp (Vp=Vreset−Vth) iscreated at node N1. However, because the voltage Vth includes an offsetvoltage (Voffset), the more correct voltage Vp is given by:VP=Vreset−(Vth+Voffset).

On the other hand, a starting voltage (Vstart) of a ramp voltage (Vramp)is applied to node N2 and, on this time, the voltage level at node N2 isVramp (=Vstart).

Also, the switches S1 and S2 are turned on and a capacitor C3 stores avoltage level of VC3. Subsequently, the switch S2 is turned offimmediately after a predetermined time to maintain such a stored voltageas shown in FIG. 9. The voltage Vc3 stored in the capacitor C3 is givenby:Vc3=Vrest=(Vth−Voffset)−Vstart

To apply an actual data from the unit pixel 120 to the comparator 220,the reset transistor Rx is tuned off and the transfer and selectiontransistors Tx and Sx are turned on so that the photocharges generatedin the photodiode are applied to a gate of the source-follow transistorDx. At this time, because the gate voltage of the source-followtransistor Dx is Vpixel, a voltage level on node N1 is Vn1(=Vpixel−(Vth+Voffset)).

Subsequently, the switches S3 and S4 are turned on and then voltagelevels of Vclamp1 and Vclamp2 are respectively induced in the capacitorsC2 and C3 based on the operation voltage of the inverting amplifiers IN1and IN2.

On the other hand, because the switch Si is continuously turned on, thecapacitors C2 and C1 respectively stores voltage levels of Vc2 and Vc1as follows:Vc2=Vpixel−(Vth+Voffset)−Vclamp1Vc1=Vclamp1−Vclamp2

In summary, the first and second stages mentioned above,‘Vreset−(Vth+Voffset)−Vstart’ is sampled at the first stage and‘Vpixel−(Vth+Voffset)−Vclamp1’ is sampled at the second stage.Accordingly, a double sampling for removing the offset voltages in thecapacitors C3 and C2 can be achieved, which is called an analogcorrelated double sampling in the present disclosure.

At the third stage, the switches S1, S3 and S4 are turned off and theswitch S2 is turned on to compare the ramp signal from the ramp signalgenerator 410 to the pixel voltage. Because the switches S1, S3 and S4are turned off, the voltage levels of the capacitor C1, C2 and C3 arekept continuous, even if the switch S2 is turned on.

At this time, the input voltage (N3) of the inverting amplifier IN1 isgiven by:VN3=Vramp+VC3−VC2=Vramp−Vstart+Vreset−Vpixel+Vclamp1

On the other hand, because the start voltage of the ramp signal isVstart, VN3 is expressed as follow:VN3=Vreset−Vpixel+Vclamp1

As shown in the above polynomial of VN3, the voltage levels of Vth andVoffset, which exist within the polynomials of VC3 and VC2, are removed;thereby achieving the analog correlated double sampling. The voltagelevel of “Vreset−Vpixel” is a net image data caused by the analog pixeldata. Also, since the voltage of Vclamp1 is an operation voltage of theinverting amplifier IN1, the comparison can be obtained while the inputvoltage of the inverting amplifier IN1 becomes Vclamp1.

A latch enable signal Latch_EN is set to a high voltage level to drivethe latch circuit 310 and a clock counting value of the counter 510increases one by one as the ramp signal from the ramp signal generator410 gradually decreases.

On the other hand, the ramp signal from the ramp signal generator 410can be expressed as follow:Vramp=Vstart−ΔV

Accordingly, the voltage level of VN3 can be expressed as follow:VN3=(Vreset−Vpixel)−ΔV+Vclamp1

According to the feature of the ramp signal, the voltage level of ΔVgradually increases with the lapse of time and eventually it is the sameas “Vreset−Vpixel.” An input voltage of the inverting amplifier IN1becomes “Vclamp1” and an input voltage of the inverting amplifier IN12becomes “Vclamp2 simultaneously, so that the two inverting amplifiersIN1 and IN2 are at the operation voltage at the same time.

This point in time is the comparison moment and, if the ramp signal isdropped a little, the signal is amplified by the gains of the invertingamplifiers IN1 and IN2 and Vo is dropped to a ground voltage level.

If Vo is dropped to the ground voltage level, the final value, which iscontinuously counted by the counter 510, is stored in the latch circuit320. Accordingly, the latched value is a digital value from the unitpixel 120.

Finally, the latch enable signal Latch_EN is set to a logic low level inorder to store the digital values in the latch circuit 320 until thedata stored to latch 310 is transmitted to the digital controller(reference numeral 500 of FIG. 1).

The current of the comparator is consumed in the inverting amplifiersIN1 and IN2 only when the comparison is carried out so that there islittle static current and it is possible to reduce the power consumptionsharply. Also, because the comparator stores the reset level in thecapacitor C3 in the analog signal level, only one ramp signal isrequired to obtain the digital signal corresponding to the input analogsignal with the simple digital control algorithm and operations used inthe CMOS image sensor. Further, because it is not necessary to store thedigital value corresponding to the reset level of the CMOS image sensor,the entire size of the memories can be reduced by half.

As apparent from the above, the disclosed comparator can reduce thefixed pattern noise, such as the offset voltage, in the CMOS imagesensor by considerably removing the offset voltage that exist betweenpixels using the analog correlated double sampling. The comparator canbe made by a simple circuit design without a subtractor because only oneramp signal is used to obtain the digital value. Also, the ramp signalgenerator for the comparison can has a simple structure so that the chipsize of the CMOS image sensor using the disclosed analog correlateddouble sampling is smaller than others using the digital correlateddouble sampling. Further, the disclosed apparatus may be employed inother integration circuits in which a low-voltage operation is requiredto reduce a power consumption or it is necessary to remove the offsetvalue to obtain an exact digital value.

The comparator may have a simple structure that connects, in series,signal processing stages to process input data and the ramp signal.Further, the disclosed device may include a CMOS inverter with alow-operation voltage and a chopper type voltage comparator. Because thechopper type voltage comparator uses an inverter as a voltage amplifier,which consumes the current only when the comparison of inputs is carriedout, the disclosed device can reduce the power consumption thereof.

The disclosure introduces a new architecture of CMOS image sensor thathas many advantages over the previous one. Such advantages includesmaller size of chip area, reduced power consumption, reduced FPN andpossibility of implementing analog gamma correction. The disclosed CMOSimage sensor is capable of reducing power consumption and a size of chipthrough the reduction of an offset voltage efficiently therein.

Although certain apparatus constructed in accordance with the teachingsof the invention have been described herein, the scope of coverage ofthis patent is not limited thereto. On the contrary, this patent coversall embodiments of the teachings of the invention fairly falling withinthe scope of the appended claims either literally or under the doctrineof equivalents.

1. A CMOS image sensor comprising: an image capturer for capturing animage and producing an analog image signal from an object; ananalog-to-digital converter for converting the analog image signal to adigital value using a ramp signal, wherein the analog-to-digitalconverter includes: a) a chopper-type comparator receiving the analogimage signal and the ramp signal; and b) a capacitor for receiving astart voltage of the ramp signal and charging a voltage levelcorresponding the start voltage of the ramp signal in a reset mode andfor receiving a down-ramping signal of the ramp signal in a count modein order to remove a device offset voltage; and a ramp signal generatorproviding the ramp signal to the analog-to-digital converter.
 2. TheCMOS image sensor as recited in claim 1, further comprising a latchcircuit for storing the digital value converted by the analog-to-digitalconverter, wherein the latch circuit has a plurality of buffer lines tostore the digital value only, wherein the capacitor is a first capacitorand wherein the chopper-type comparator comprises: a plurality ofcapacitors and switches; and at least two inverting amplifiers, whereinthe switches are controlled by a digital controller in the CMOS imagesensor.
 3. The CMOS image sensor as recited in claim 1, wherein thecapacitor is a first capacitor and wherein the chopper-type comparatorcomprises: a plurality of capacitors and switches; and at least twoinverting amplifiers, wherein the switches are controlled by a digitalcontroller in the CMOS image sensor.
 4. The CMOS image sensor as recitedin claim 3, wherein the chopper-type comparator comprises: a firstswitch connected to the image capturer; a second switch connected to theramp signal generator; a second capacitor connected to the first switch,wherein the first capacitor is connected between the first switch andthe second switch; a first inverting amplifier connected to the secondcapacitor; a third switch connected between input and output terminalsof the first inverting amplifier; a third capacitor connected to thefirst inverting amplifier; a fourth switch connected between input andoutput terminals of the a second inverting amplifier; and awherein thesecond inverting amplifier is connected to the third capacitor and thelatch circuit to store the digital value.
 5. The CMOS image sensor asrecited in claim 4, wherein the first switch is turned on in response toa control signal from the digital controller in the rest reset mode andin a charge transfer mode in which photocharges are transferred to theanalog-to-digital converter.
 6. The CMOS image sensor as recited inclaim 5, wherein the first, third, and fourth switches are turned on inresponse to a control signal from the digital controller in the chargetransfer mode in which photocharges are transferred to theanalog-to-digital converter.
 7. A method for removing a device offsetvoltage in a CMOS image sensor, the method comprising: charging a startvoltage of a ramp signal in a capacitor and simultaneously charging arest reset voltage of an image capturer in a chopper-type comparator ina reset mode; providing to the chopper-type comparator an analog imagesignal from the image capturer in a charge transfer mode; and providinga down-ramping signal of the ramp signal to the chopper-type comparatorin a count mode.
 8. A CMOS image sensor comprising: an image capturerincluding a plurality of pixel sensor circuits configured to provideanalog signals in a reset mode and a read mode, wherein each pixelsensor circuit is further configured to provide a reset signal in thereset mode and a pixel output signal in the read mode, and wherein anoffset signal is superimposed on the reset signal and the pixel outputsignal of each pixel sensor circuit; a ramp signal generator configuredto provide a ramp signal, wherein the ramp signal includes a ramp signalwaveform beginning as a start signal; a chopper circuit configured toreceive the analog signals and the ramp signal, wherein the choppercircuit is further configured to generate a control signal to controloperation of a logic component, and wherein the chopper circuit isfurther configured such that: during the reset mode, the chopper circuitgenerates a reset mode signal corresponding to a difference betweenfirst and second signals, wherein the first signal includes the resetsignal, wherein the second signal includes a sum of the offset signaland the start signal, and wherein the reset signal, offset signal, andstart signal are sampled concurrently; during the read mode, the choppercircuit generates a clamped logic level signal, wherein the choppercircuit further generates a read mode signal that corresponds to adifference between the pixel output signal and a third signal, andwherein the third signal includes a sum of the offset signal and theclamped logic level signal; and during the read mode, the choppercircuit generates the control signal using a signal corresponding to adifference between the reset mode signal and the read mode signal. 9.The CMOS image sensor of claim 8, wherein the ramp signal waveformincludes a down-ramping waveform.
 10. The CMOS image sensor of claim 8,wherein the chopper circuit comprises: a plurality of capacitors andswitches; and at least two inverting amplifiers, wherein the switchesare configured to respond to control signals provided by a digitalcontroller in the CMOS image sensor.
 11. The CMOS image sensor of claim10, wherein the chopper circuit further comprises: a first switchconfigured to receive the analog signals from the image capturer; asecond switch configured to receive the ramp signal from the ramp signalgenerator; a first capacitor connected between the first switch and thesecond switch; a first inverting amplifier connected to the firstcapacitor; a third switch connected between input and output terminalsof the first inverting amplifier; a second capacitor connected betweenthe first switch and the input terminal of the first invertingamplifier; a second inverting amplifier; a third capacitor connectedbetween the output terminal of the first inverting amplifier and aninput terminal of the second inverting amplifier; a fourth switchconnected between input and output terminals of the second invertingamplifier; wherein the output terminal of the second inverting amplifieris provided as the control signal from the chopper circuit.
 12. The CMOSimage sensor of claim 11, wherein the first, second, third, and fourthswitches are configured to respond to control signals from the digitalcontroller.
 13. The CMOS image sensor of claim 8, further comprising alatch circuit configured to store a digital value of a digital counterif a difference between the reset mode signal and the read mode signalcorresponds to a magnitude of the ramp signal waveform.
 14. A method ofcompensating for an offset voltage of a pixel sensor in a CMOS imagesensor, the method comprising: providing a reset voltage from the pixelsensor during a reset mode, wherein the offset voltage is superimposedon the reset voltage; providing a ramp voltage waveform beginning at astart voltage; concurrently sampling the reset voltage, the offsetvoltage superimposed on the reset voltage, and the start voltage;generating a reset mode voltage, wherein the reset mode voltagecorresponds to a difference between first and second voltages, whereinthe first voltage includes the reset voltage, and wherein the secondvoltage includes a sum of the offset voltage and the start voltage;generating a clamped logic level voltage; providing a pixel outputvoltage during a pixel sensor read mode, wherein the offset voltage issuperimposed on the pixel output voltage; generating a read mode voltagecorresponding to a difference between the pixel output voltage and athird voltage, wherein the third voltage includes a sum of the offsetvoltage and the clamped logic level voltage; and generating a controlsignal to a logic circuit, wherein the control signal corresponds to adifference between the reset mode voltage and the read mode voltage. 15.The method of claim 14, wherein said generating a reset mode voltagecomprises: configuring a capacitor to receive the reset voltage and theoffset voltage at a first terminal; and configuring the capacitor toreceive the start signal at a second terminal.
 16. A CMOS image sensorcomprising: an image capturer including a plurality of pixel sensorcircuits, wherein each pixel sensor circuit is configured to provide areset signal in a reset mode and a pixel output signal in a read mode,and wherein an offset signal is superimposed on the reset signal and thepixel output signal of each pixel sensor circuit during the reset modeand read mode, respectively; a ramp signal generator configured toprovide a ramp signal, wherein the ramp signal includes a ramp signalwaveform beginning as a start signal; a chopper circuit configured toreceive the reset signal with the superimposed offset signal from agiven pixel sensor circuit during the reset mode and the pixel outputsignal with the superimposed offset signal from the given pixel sensorcircuit during the read mode, wherein the chopper circuit is configuredto receive the ramp signal from the ramp signal generator, and whereinthe chopper circuit is configured to generate a control signal tocontrol operation of a logic component; wherein, during the reset mode,the chopper circuit is configured to generate a reset mode signal acrossa charging element by concurrently sampling the reset signal and theoffset signal from the given pixel sensor circuit and the start signalfrom the ramp signal generator, wherein the reset mode signalcorresponds to a difference between first and second signals, andwherein the first signal includes the reset signal, and wherein thesecond signal includes a sum of the offset signal and the start signal;wherein, during the read mode, the chopper circuit is further configuredto generate a clamped logic level signal and is further configured togenerate a read mode signal that corresponds to a difference between thepixel output signal and a third signal, wherein the third signalincludes a sum of the offset signal and the clamped logic level signal;and wherein, during the read mode, the chopper circuit is furtherconfigured to generate the control signal using a signal correspondingto a difference between the reset mode signal and the read mode signal.17. The CMOS image sensor of claim 16, wherein the charging elementcomprises a capacitor connected between first and second inputs of thechopper circuit.
 18. A CMOS image sensor comprising: an image capturerhaving a plurality of pixel sensor circuits, wherein each pixel sensorcircuit is configured to provide an analog signal at its output; a rampsignal generator configured to provide a ramp signal; a chopper circuitconfigured to receive the analog signal from a given pixel sensorcircuit and to receive the ramp signal from the ramp signal generator,wherein the chopper circuit is configured to: provide a logic levelcontrol signal to control operation of a logic component, wherein thelogic level control signal is used to generate a digital signalcorresponding to a magnitude of the analog signal provided from theoutput of the given pixel sensor circuit; and store a signal across acharging element, wherein the signal stored across the charging elementcorresponds to a difference between the analog signal from the givenpixel sensor circuit and the ramp signal from the ramp signal generator,wherein the analog signal from the given pixel sensor circuit and theramp signal from the ramp signal generator are concurrently sampled tostore the signal across the charging element during a mode of at leasttwo modes of operation of the given pixel sensor circuit to generate thelogic level control signal to the logic component, wherein the chargingelement comprises a capacitor connected between first and second inputsof the chopper circuit.
 19. The CMOS image sensor of claim 18, whereinthe at least two modes of operation comprise a reset mode in which areset signal is provided from the output of the given pixel sensorcircuit and a read mode in which a pixel output signal is provided fromthe output of the given pixel sensor circuit.